首页> 外国专利> METHOD AND APPARATUS FOR REDUCING ELECTRICAL RESONANCES AND NOISE PROPAGATION IN POWER DISTRIBUTION CIRCUITS EMPLOYING PLANE CONDUCTORS

METHOD AND APPARATUS FOR REDUCING ELECTRICAL RESONANCES AND NOISE PROPAGATION IN POWER DISTRIBUTION CIRCUITS EMPLOYING PLANE CONDUCTORS

机译:减少使用平面导体的配电电路中的谐振和噪声传播的方法和装置

摘要

Electrical resonances are reduced and noise propagation is attenuated in a multi-layer construction using planar power and ground planar conductors separated by insulating material by loading the power and ground planar conductors with a sufficient amount of capacitance, or series capacitance and resistance, at specific locations so that the planar conductors are electrically broken up into smaller sections which resonate at frequencies above the signal bandwidth. The propagation of injected noise is suppressed by the low-pass filter effect of the capacitive loading at the discrete locations. In accordance with one embodiment of the invention, islands of material with a dielectric constant higher than the dielectric constant of the overall insulator are placed at regular intervals where the capacitance of each high dielectric constant island is comparable to, or higher than, the capacitance of the “low” dielectric material which comprises the remainder of the insulating material. In accordance with a second embodiment, high dielectric constant islands are placed around power and ground vias where most of the transient charge capability is needed.
机译:在平面结构中使用平面电源和接地平面导体(通过绝缘材料隔开),通过在特定位置加载足够量的电容(或串联电容和串联电容)或串联电容和电阻,可减少电气共振并降低噪声传播因此,平面导体被电分解成较小的部分,这些部分在高于信号带宽的频率处发生谐振。离散位置处的电容性负载的低通滤波器效应抑制了注入噪声的传播。根据本发明的一个实施例,将介电常数高于整个绝缘体的介电常数的材料的岛以规则的间隔放置,其中每个高介电常数岛的电容可等于或高于其介电常数。 “低”包括其余绝缘材料的介电材料。根据第二实施例,在需要大多数瞬时充电能力的电源和接地通孔周围放置高介电常数岛。

著录项

  • 公开/公告号EP1186213A1

    专利类型

  • 公开/公告日2002-03-13

    原文格式PDF

  • 申请/专利权人 SUN MICROSYSTEMS INC.;

    申请/专利号EP20000938092

  • 发明设计人 NOVAK ISTVAN;

    申请日2000-06-02

  • 分类号H05K1/16;

  • 国家 EP

  • 入库时间 2022-08-22 00:33:49

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