Method and Apparatus For Reducing Power In Cache Memories And A Data Prcoessing System having Cache memories

摘要

The present invention provides a digital data processing system comprising a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling access to the cache memory. The controller stores state information about the type of access, mode of operation, and cache hit / miss associated with the most recent access to the tag RAM. The controller stores some of the previous access-related state information and some of the set fields of the main memory address that you want to access. On the basis of this, it controls the current access to the tag RAM. The controller determines whether the current access is the same as the cache line that was previously accessed, based on some of the previous access-related state information and some of the set fields of the main memory address for the current access, and the current access is also accessed immediately. When it is equal to one cache line, access to the tag RAM can be skipped.