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Method and apparatus for reducing power in cache memories and a data processing system having cache memories
Method and apparatus for reducing power in cache memories and a data processing system having cache memories
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机译:用于减少高速缓冲存储器中的功率的方法和装置以及具有高速缓冲存储器的数据处理系统
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摘要
A digital data processing system is provided which includes a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling accesses to the cache memory. The controller stores state information on access type, operation mode and cache hit/miss associated with the most recent access to the tag RAM, and controls a current access to the tag RAM just after the preceding access based on the state information and a portion of a set field of a main memory address for the second access. The controller determines whether the current access is applied to the same cache line that was accessed in the first access based on the state information and a portion of a set field of the main memory address for the second access, and allows the current access to be skipped when the current access is applied to the same cache line that was accessed in the preceding access.
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