METHOD AND APPARATUS FOR FACILITATING MUTIPLE STORAGE INSTRUCTION COMPLETIONS IN A SUPERSCALAR PROCESSOR DURING A SINGLE CLOCK CYCLE

摘要

One feature of the present invention is to complete the instructions in order and on a superscalar processor including a processor having an instruction dispatch unit, an archived register file, a rename register file, a load storage unit, a completion unit, and a cache memory. A device for processing storage instructions. In one embodiment of the present invention, an apparatus of the present invention includes a pointer queue having an entry corresponding to a storage instruction, a structured register file containing data required by the storage instruction, and a pointer to an entry in the rename register file. And an multiplexer coupled to the read port on the structured register file and the rename register file to allow data to be transferred from one of the register files to an entry in the data queue coupled to cache memory.