INTELLIGENT GATE-LEVEL FILL METHODS FOR REDUCING GLOBAL PATTERN DENSITY EFFECTS

摘要

The present invention provides a method for intelligently filling a gate layer in a dummy fill pattern to produce a target pattern density. A gate layout defining a gate region on a gate layer on a semiconductor substrate is provided with a diffusion layout defining an active diffusion region. For the gate layout, the pattern density is determined. Then, the regions that are not occupied by the gate region and the diffusion region are determined. Additionally, a range of pattern densities is provided in a set of predefined fill patterns having a plurality of dummy fill patterns and each having a predefined fill pattern associated with the pattern density within the range of pattern densities provided. During the predefined set of fill patterns, a predefined fill pattern is selected to create the target pattern density. The gate layer is then filled by placing a dummy fill pattern of the selected predefined fill pattern in the unoccupied area by the gate area and the diffusion area. Thus, the target pattern density is provided in the gate layer when combined with the pattern density of the gate layout.