WIDE TRACKING RANGE AUTO RANGING LOW JITTER PHASE LOCK LOOP FOR SWEPT AND FIXED FREQUENCY SYSTEMS

摘要

PURPOSE: A wide tracking range PLL(Phase Locked Loop) circuit is provided to achieve minimal jitter in a recovered clock signal, regardless of the source of the jitter. CONSTITUTION: The PLL circuit(20) comprises automatic harmonic lockout detection circuitry via a novel lock and seek control logic(33) in electrical communication with a programmable frequency discriminator(35) and a code balance detector(36). In addition, the combination of a differential loop integrator(57) with the lock and seek control logic(33) obviates a code preamble and guarantees signal acquisition without harmonic lockup. An adaptive cable equalizer(31) is desirably used in combination with the PLL to recover encoded transmissions containing a clock and/or data. The equalizer(31) automatically adapts to equalize short haul cable lengths of coaxial and twisted pair cables or wires and provides superior jitter performance. The combination of the equalizer(31) with the PLL is desirable in that such combination permits the use of short haul wires without significant jitter.