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Output driver for reducing a slewing rate variation of output data in semiconductor device and reducing method of slewing rate variation

机译:用于减小半导体器件中的输出数据的转换速率变化的输出驱动器以及减小转换速率变化的方法

摘要

PURPOSE: An output driver for reducing a variation of a slewing rate of output data in a semiconductor device and a method for reducing a variation of slewing data are provided to reduce the variation of slewing rate of output data by improving a structure of an output driver circuit. CONSTITUTION: The supply voltage(VDD) is applied to a source of an output PMOS transistor. The first output data are applied to a gate of the output PMOS transistor. A source of compensating PMOS transistor is connected with a drain of the output PMOS transistor. The second compensating voltage is applied to a gate of the compensating PMOS transistor. A drain of the compensating PMOS transistor is connected with an output node(DN). A compensating NMOS transistor has a drain connected with the output node(DN) and a gate for receiving the second compensating voltage. The compensating PMOS transistor and the compensating NMOS transistor reduce the variation of slewing rates of the first output data(DATA1) and the second output data(DATA2). An output NMOS transistor has a drain connected with the source of the compensating NMOS transistor, a gate for receiving the second output data(DATA2), and a source connected with a ground.
机译:目的:提供一种用于减小半导体器件中的输出数据的转换率的变化的输出驱动器和一种用于减小转换数据的变化的方法,以通过改善输出驱动器的结构来减小输出数据的转换率的变化。电路。组成:电源电压(VDD)施加到输出PMOS晶体管的源极。第一输出数据被施加到输出PMOS晶体管的栅极。补偿PMOS晶体管的源极与输出PMOS晶体管的漏极连接。将第二补偿电压施加到补偿PMOS晶体管的栅极。补偿PMOS晶体管的漏极与输出节点(DN)连接。补偿NMOS晶体管具有与输出节点(DN)连接的漏极和用于接收第二补偿电压的栅极。补偿PMOS晶体管和补偿NMOS晶体管减小了第一输出数据(DATA1)和第二输出数据(DATA2)的转换速率的变化。输出NMOS晶体管具有与补偿NMOS晶体管的源极连接的漏极,用于接收第二输出数据(DATA2)的栅极以及与地连接的源极。

著录项

  • 公开/公告号KR20020054893A

    专利类型

  • 公开/公告日2002-07-08

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20000084158

  • 发明设计人 SHIN SUN GYUN;

    申请日2000-12-28

  • 分类号G11C7/10;

  • 国家 KR

  • 入库时间 2022-08-22 00:30:40

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