METHOD FOR INTEGRATED DECODING AND INTEGRATED DECODER OF VITERBI DECODER AND TURBO DECODER

摘要

PURPOSE: An integrated decoder of a Viterbi decoder and a turbo decoder and a method for performing an integrated decoding process are provided to reduce complexity of a hardware and economize a memory source by forming a Viterbi decoder and a turbo decoder with one body. CONSTITUTION: An 8-state SOVA/256-state Viterbi decoder(80) is formed by including a hard decision Viterbi decoder in a SOVA decoder of a turbo decoder. The 8-state SOVA/256-state Viterbi decoder(80) has an integrated structure of the 8-state SOVA decoder and the Viterbi decoder. In a Viterbi decoder mode, the 8-state SOVA/256-state Viterbi decoder(80) transmits an output to an output terminal since 8-state SOVA/256-state Viterbi decoder(80) does not use necessary parts used in a repetition decoding process of the turbo decoder. In a turbo decoding mode, the repetition decoding process is performed by processing 8 states at once.