We present a mixed-signal VLSI architecture for state-parallel analog Viterbi decoding, including an analog Add-Compare-Select (ACS) module and a digital survivor path memory (PM) module. A single-chip 64-state analog Viterbi decoder for K=7 convolutional code has been implemented in 3.3 V 0.5 /spl mu/m CMOS technology. The chip measures 5.05/spl times/2.54 mm/sup 2/, and achieves a decoding speed of 40 Mb/s (20 MHz clock) at 50 mW power consumption as verified by post-layout transistor-level simulation. In addition, a behavioral model accounting for inaccuracies in the analog implementation is developed to simulate the bit error rate (BER) vs. signal-to-noise (SNR) performance, confirming superior error correction (coding gain) of the mixed-signal design over hard-decision and 3-bit soft-decision digital implementations.
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机译：我们提出了一种用于状态并行模拟维特比解码的混合信号VLSI架构，包括模拟加比较选择（ACS）模块和数字幸存者路径存储器（PM）模块。采用3.3 V 0.5 / spl mu / m CMOS技术实现了用于K = 7卷积码的单芯片64状态模拟Viterbi解码器。该芯片的尺寸为5.05 / spl倍/2.54 mm / sup 2 /，并且在功耗为50 mW时达到了40 Mb / s（20 MHz时钟）的解码速度，这一点已通过布局后晶体管级仿真得到了验证。此外，开发了一种模拟模型实现中不准确的行为模型，以模拟误码率（BER）与信噪比（SNR）性能，从而确认了混合信号设计的出色纠错能力（编码增益）超过硬决策和3位软决策数字实现。
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