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Semiconductor memory device including chip selection circuit and method for generating chip selection signal

机译:包括芯片选择电路的半导体存储器件和用于产生芯片选择信号的方法

摘要

PURPOSE: A semiconductor memory device having a chip selection circuit and a method for generating a chip selection signal are provided to analyze a cause of a bad semiconductor memory device and improve the quality of the semiconductor memory device by selecting only a selected particular memory device such as a bad memory device. CONSTITUTION: An address register(11) receives an address(ADD) from an outside of a semiconductor memory device and outputs the received address to a programming register(13). A timing register(12) receives a command(CMD) from an outside of a semiconductor memory device and outputs the received command to the programming register(13). The programming register(13) activates its own output signal(MRSi) in response to the address of the address register(11) and the command of the timing register(12). An input buffer control circuit(14) activates its own output signal(Buff_on) and data input buffer circuits(15_0 to 15_n) in response to activation of the output signal(MRSi) of the programming register(13). A chip selection circuit(16) activates a chip selection signal(CMSS) and an error verification and improvement circuit(17) when one or more output signals(Output_0 to Output_n) of the data input buffers(15_0 to 15_n) are in a state of the first logic. The error verification and improvement circuit(17) are formed by a repair circuit or a test time reduction circuit.
机译:目的:提供一种具有芯片选择电路的半导体存储器件及其产生芯片选择信号的方法,以通过仅选择所选择的特定存储器件来分析半导体存储器件损坏的原因并提高半导体存储器件的质量。作为坏的存储设备。组成:地址寄存器(11)从半导体存储设备的外部接收地址(ADD),并将接收到的地址输出到编程寄存器(13)。定时寄存器(12)从半导体存储器件的外部接收命令(CMD),并将接收到的命令输出到编程寄存器(13)。编程寄存器(13)响应于地址寄存器(11)的地址和定时寄存器(12)的命令来激活其自己的输出信号(MRSi)。输入缓冲器控制电路(14)响应于编程寄存器(13)的输出信号(MRSi)的激活而激活其自身的输出信号(Buff_on)和数据输入缓冲器电路(15_0至15_n)。当数据输入缓冲器(15_0至15_n)的一个或多个输出信号(Output_0至Output_n)处于状态时,芯片选择电路(16)激活芯片选择信号(CMSS)以及错误验证和改善电路(17)。第一种逻辑。误差验证和改善电路(17)由修复电路或测试时间减少电路形成。

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