2 Semiconductor device in which MPU and DRAM as secondary cache memory are mounted on same chip to easily realize high speed of cycle time under restriction on chip size

摘要

A semiconductor device, MPU (micro processing unit) provided with portions, DRAM (dynamic random access memory) unit, a plurality of address registers, and a plurality of address delay compensation. MPU unit is provided on the chip and outputs the clock signal and an address signal. DRAM portion is provided on a chip to input a clock signal and an address signal. Each of the plurality of address registers and latches an address signal in response to the clock signal. Each of the plurality of address delay compensation unit compensates for the address signal is provided to the front end transmission delay address signal transmission delay time to fall within a predetermined range of said plurality of address registers. Address signal transmission delay represents an elapsed time until the input of the MPU portion and the address signal is the address signal, each said address register after the output.