Simultaneous Switching Noise Minimization Technique for Power Lines using Dual Layer Power Line Mutual Inductors

摘要

The present invention minimizes the noise caused by parasitic inductor components present on the PCB board operating at high speed, or minimizes noise generated in the power line by simultaneous operation of large buffers connected to the output pads on the on-chip of the integrated circuit. To minimize, the pull-up transistor (M ₁ ) and pull-down transistor (M ₂ ) are divided in half, respectively, the pull-up transistor (M ₁₁ ), the pull-down transistor (M ₂₁ ), the pull-up transistor (M ₁₂ ) and the pull-down transistor (M ₂₂ ). Are formed respectively, and the pull-up transistor (M ₁₁ ), the pull-down transistor (M ₂₁ ), and the pull-up transistor (M ₁₂ ) and the pull-down transistor (M ₂₂ ) are adjacent to each other having the same width and flow in opposite directions, respectively. 1 by being respectively connected between the power line (V _DD1, V _SS1) and the second power line (V _DD2, V _SS2), a noise caused by simultaneous operation of the buffer at least Is an error of the output data is minimized, it is possible to increase the speed, the structure is easy to Im invention with the advantage of not taking up additional area.