Address generator for generating addresses for on-chip trimming circuit, has memory latch stages for operation as counter synchronized to control signal or clock signal or as shift register

摘要

The address generator (10) has a defined number of stages, where the number exceeds one, each consisting of a memory latch for operation as a counter synchronized to a control signal fed to a control input (5,6) of the address generator or a clock signal fed to its clock input (14) or as a shift register. The address generator (10) has a defined number of stages, where the number exceeds one, each consisting of a memory latch for operation as a counter synchronized to a control signal fed to a control input (5,6) of the address generator or a clock signal fed to its clock input (14) or as a shift register. The address generator has electrical fuses in which addresses generated for the trim circuit are stored if a variable reference voltage coincides with an external comparison voltage. The level of address information to be fed to the fuses is adapted to CMOS level.