首页> 外国专利> Integrated circuit used in DRAMs and SDRAMs comprises a switching element formed in a substrate, a further switching element buried in the substrate, and an insulating layer lying between the elements and locally limited in the substrate

Integrated circuit used in DRAMs and SDRAMs comprises a switching element formed in a substrate, a further switching element buried in the substrate, and an insulating layer lying between the elements and locally limited in the substrate

机译:DRAM和SDRAM中使用的集成电路包括:形成在衬底中的开关元件;另外的埋入衬底中的开关元件;以及位于元件之间并局部限制在衬底中的绝缘层

摘要

Integrated circuit comprises: a switching element (AT) formed in a substrate (1); a switching element (160) buried in the substrate away from the element (AT); and an insulating layer (7) lying between the elements and locally limited in the substrate. An Independent claim is also included for a process for the production of an integrated circuit, comprising forming trenches (10) in a substrate (1), forming an outer conducting layer on lower regions of the trenches within the substrate as first capacitor plates, forming dielectric layers in the trenches as capacitor dielectric, forming an inner conducting layer (5) in the trenches as second capacitor plates, and forming insulating areas (7) on wall sections of the trenches above the outer conducting layer. Preferred Features: The insulating layer is a thermal oxide. The substrate is a single crystalline semiconductor substrate.
机译:集成电路包括:形成在基板(1)中的开关元件(AT);以及开关。掩埋在远离元件(AT)的衬底中的开关元件(160);绝缘层(7)位于元件之间并局部地限制在基板中。还包括关于集成电路生产工艺的独立权利要求,包括:在衬底(1)中形成沟槽(10),在衬底内的沟槽的下部区域上形成外部导电层作为第一电容器板,形成沟槽中的电介质层作为电容器电介质,在沟槽中形成内部导电层(5)作为第二电容器板,并在外部导电层上方的沟槽的壁部分上形成绝缘区域(7)。优选特征:绝缘层是热氧化物。衬底是单晶半导体衬底。

著录项

  • 公开/公告号DE10030696A1

    专利类型

  • 公开/公告日2002-01-10

    原文格式PDF

  • 申请/专利权人 INFINEON TECHNOLOGIES AG;

    申请/专利号DE2000130696

  • 发明设计人 LUETZEN JOERN;SELL BERNHARD;

    申请日2000-06-23

  • 分类号H01L21/762;H01L21/8242;H01L27/108;

  • 国家 DE

  • 入库时间 2022-08-22 00:27:41

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