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Structure for reducing a voltage drop along a word/bit line operates during the reading of a memory cell in an MRAM memory's memory cell field with the memory cell placed at an intersecting point between selected word and bit lines.
Structure for reducing a voltage drop along a word/bit line operates during the reading of a memory cell in an MRAM memory's memory cell field with the memory cell placed at an intersecting point between selected word and bit lines.
Both ends of a selected word line (WL2) are set at a high voltage (V2) to keep the voltage drop on the selected word line as low as possible. A cell (Z22) is read out at an intersecting point between the selected word line and a bit line. Other word lines are set at another voltage level. An Independent claim is also included for a method for reducing the voltage drop along a word/bit line in an MRAM memory.
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