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Selective division circuit for cryptographic applications has multiplexer outputs coupled to different groups of multiplexer outputs when division is not required and required respectively
Selective division circuit for cryptographic applications has multiplexer outputs coupled to different groups of multiplexer outputs when division is not required and required respectively
The selective division circuit has a multiplexer (100) with twice the number of inputs (102) than the number of outputs (104) and a multiplexer control (112), connecting the outputs to a first group of inputs (102a) when no division is required and to a second group of inputs (102b) when the number division is required. An Independent claim for a processor with a system bus coupled to a selective division circuit is also included.
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