首页> 外国专利> Selective division circuit for cryptographic applications has multiplexer outputs coupled to different groups of multiplexer outputs when division is not required and required respectively

Selective division circuit for cryptographic applications has multiplexer outputs coupled to different groups of multiplexer outputs when division is not required and required respectively

机译:用于加密应用的选择性除法电路在不需要和分别需要除法时,将多路复用器输出耦合到不同组的多路复用器输出

摘要

The selective division circuit has a multiplexer (100) with twice the number of inputs (102) than the number of outputs (104) and a multiplexer control (112), connecting the outputs to a first group of inputs (102a) when no division is required and to a second group of inputs (102b) when the number division is required. An Independent claim for a processor with a system bus coupled to a selective division circuit is also included.
机译:选择性除法电路具有输入(102)的数量是输出(104)的数量的两倍的多路复用器(100)和多路复用器控制(112),当不进行除法时,将输出连接到第一组输入(102a)当需要数字除法时,输入到第二组输入(102b)。还包括对具有耦合到选择性分割电路的系统总线的处理器的独立权利要求。

著录项

  • 公开/公告号DE10108916C1

    专利类型

  • 公开/公告日2002-07-25

    原文格式PDF

  • 申请/专利权人 INFINEON TECHNOLOGIES AG;

    申请/专利号DE2001108916

  • 发明设计人 BOCK HOLGER;HOFER ROBERT;

    申请日2001-02-23

  • 分类号G06F7/52;

  • 国家 DE

  • 入库时间 2022-08-22 00:27:07

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