Dimensioning transistors in integrated circuits by re-dimensioning transistors in path with propagation time below target, based on propagation time probability distribution

摘要

The method involves creating a circuit design for the integrated circuit comprising a number of paths, where a path includes a serial arrangement of transistor gates. The nominal propagation time of the paths are determined based on the initial dimensioning of the transistors of the paths. The method then involves determining at least one path to be optimized, whose nominal path propagation time lies below a target propagation time (Tziel). The transistors of the path to be optimized are re-dimensioned, taking account of a gate propagation time probability distribution and the number of transistor gates in the path.