首页> 外国专利> Semiconductor device, such as fusible link semiconductor memory device, has fusible link circuit with its fusible link in series with an assessment transistor having a controlled impedance path

Semiconductor device, such as fusible link semiconductor memory device, has fusible link circuit with its fusible link in series with an assessment transistor having a controlled impedance path

机译:诸如熔断链路半导体存储设备之类的半导体器件具有熔断电路,其熔断电路与具有受控阻抗路径的评估晶体管串联。

摘要

Semiconductor device with fusible link assessment circuit in which the fusible link assessment circuit includes at least one programmable fusible link arranged in series with a controlled impedance path, and a control circuit which changes the impedance of the controlled impedance path, specifically by changing a control node potential.
机译:具有熔断链路评估电路的半导体器件,其中所述熔断链路评估电路包括至少一个与受控阻抗路径串联布置的可编程熔断链路,以及改变所述受控阻抗路径的阻抗的控制电路,特别是通过改变控制节点潜在。

著录项

  • 公开/公告号DE10121459A1

    专利类型

  • 公开/公告日2001-11-22

    原文格式PDF

  • 申请/专利权人 NEC CORP. TOKIO/TOKYO;

    申请/专利号DE2001121459

  • 发明设计人 OIKAWA TAKESHI;

    申请日2001-05-02

  • 分类号G11C17/16;

  • 国家 DE

  • 入库时间 2022-08-22 00:26:58

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