Method of modeling system design for VLSI CAD by arranging event nodes defined for samples in hierarchical levels

摘要

The method involves defining at least one cell describing a device in the system, defining one or more samples of the cell that describe devices that are sued to form the functionality of the cell. Event nodes are defined for each of the samples. The event nodes are arranged in one or more hierarchical levels. Each event nodes may comprise specific event data. Independent claims are also included for: (a) a method for defining and analyzing a system defined by a nested model. (b) a method of delivering event nodes for simple nesting models