System and method for determining a highest level signal name in a hierarchical VLSI design

摘要

Systems, methods, and software products determine a highest level signal name in a hierarchical circuit design. A signal path is traced into a hierarchically lower level of the circuit design from a predetermined net in the circuit design to a predetermined terminal instance, while adding indicia, to an instance history list, of each subsequent instance encountered. A port instance is determined on the terminal instance associated with a selected net for which the highest level signal name is to be determined. The selected net is designated as the current net. For each stored indicia in the instance history list, the net connected to the current net in a hierarchical parent of the instance identified by the indicia is determined, to establish a next current net. If a condition exists wherein there is no connection from the current net to a hierarchically higher level instance, then the current net is established as the highest level signal name for the selected net.