首页> 外国专利> Circuit for delaying the modulation of fm - signals

Circuit for delaying the modulation of fm - signals

机译:延迟fm信号调制的电路

摘要

PROBLEM TO BE SOLVED: To satisfactorily eliminate the higher harmonics even with use of an LPF that has the comparatively slow blocking characteristic by converting the frequency of the higher harmonic of the demodulation signal contained in an arithmetic output signal into the higher frequency. ;SOLUTION: A limiter amplifier 11 applies the amplitude limit amplification to an input signal S11 that undergone the FM modulation. The 1st to 3rd delay circuits 12 to 14 produce the 1st to 3rd signals S13 to S15 which are delayed against the signal S12 by a time (preferably 1/8, 1/4, 3/8, etc.) that is successively increased within a time shorter than 1/2 signal cycle that is set when the output signal S12 of the amplifier 11 is shifted by the maximum frequency in the positive direction. The signal S12 is multiplied by the signal S13 by a 1st multiplier circuit 15, and the signal S14 is multiplied by the signal S15 by a 2nd multiplier circuit 16. Then the output signal S16 of the circuit 15 is added to the output signal S17 by an adder circuit 17.;COPYRIGHT: (C)1997,JPO
机译:解决的问题:即使通过使用具有相对较慢的阻塞特性的LPF,也可以通过将算术输出信号中包含的解调信号的高次谐波的频率转换为较高的频率,来令人满意地消除高次谐波。 ;解决方案:限幅放大器11将幅度限制放大应用于经过FM调制的输入信号S11。第一至第三延迟电路12至14产生第一至第三信号S13至S15,该信号相对于信号S12延迟了一定时间(优选为1 / 8、1 / 4、3 / 8等),该时间在此范围内依次增加。该时间小于当放大器11的输出信号S12在正方向上偏移最大频率时所设置的1/2信号周期的时间。信号S12通过第一乘法器电路15与信号S13相乘,信号S14通过第二乘法器电路16与信号S15相乘。然后,电路15的输出信号S16通过以下方式与输出信号S17相加:加法器电路17 .;版权:(C)1997,JPO

著录项

  • 公开/公告号DE69613790T2

    专利类型

  • 公开/公告日2002-05-16

    原文格式PDF

  • 申请/专利权人 KABUSHIKI KAISHA TOSHIBA KAWASAKI;

    申请/专利号DE1996613790T

  • 发明设计人 ADACHI MICHIHIRO;

    申请日1996-10-18

  • 分类号H03D3/06;

  • 国家 DE

  • 入库时间 2022-08-22 00:25:21

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号