Digital continuous phase modulation for a by a direct digital synthesizer controlled phase locked loop

• 1. 电流输出控制装置及方法、数字控制振荡装置、数字锁相环、频率合成器及数字频率锁定环 [P] . 中国专利： CN103475364B . 2017.12.15
• 2. 电流输出控制装置及方法、数字控制振荡装置、数字锁相环、频率合成器及数字频率锁定环 [P] . 中国专利： CN103475364A . 2013-12-25
• 3. DIRECT DIGITAL FREQUENCY SYNTHESIZER AND A HYBRID FREQUENCY SYNTHESIZER COMBINING A DIRECT DIGITAL FREQUENCY SYNTHESIZER AND A PHASE LOCKED LOOP [P] . CA2349478C . 2004-08-24

  机译： 直接数字频率合成器和混合频率合成器，将直接数字频率合成器和锁相环相结合

• 4. Direct digital frequency synthesizer and a hybrid frequency synthesizer combining a direct digital frequency synthesizer and a phase locked loop [P] . 美国专利： US6483388B2 . 2002-11-19

  机译： 直接数字频率合成器和结合了直接数字频率合成器和锁相环的混合频率合成器

• 5. Direct digital frequency synthesizer and a hybrid frequency synthesizer combining a direct digital frequency synthesizer and a phase locked loop [P] . 美国专利： US2002008588A1 . 2002-01-24

  机译： 直接数字频率合成器和结合了直接数字频率合成器和锁相环的混合频率合成器

• 1. Novel analysis method for the spurious spectrum of direct digital frequency synthesizer in the presence of phase truncation [J] . Xie Renhong, Shi Xiangquan 系统工程与电子技术（英文版） . 2005,第002期
• 2. Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop [J] . Hongchen Jiao, Tao Wang, Heli Gao, 光学与光子学期刊（英文） . 2021,第008期
• 3. THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS [J] . Deng Xiaoying, Yang Jun, Shi Longxing, 电子科学学刊（英文版） . 2008,第005期
• 4. An all-digital frequency locked loop (ADFLL) with a pulse output direct digital frequency synthesizer (DDFS) and an adaptive phase estimator [C] . Gothandaraman, A., Islam, . 2003
• 5. A low complexity digital phase-locked loop based frequency synthesizer. [D] . Zhuang, Jingcheng. 2008
• 6. A Digital Constant-Frequency Pulsed Phase-Locked-Loop Instrument for Real-Time Absolute Ultrasonic Phase Measurements [O] . Harold A. Haldren, Mool C. Gupta, Daniel F. Perey, -1
• 7. Numerically Controlled Phase Locked Loop Using Direct Digital Synthesizer [O] . A., Pei 1993

• 1. A Digital Phase Locked Loop Speed Control of Three Phase Induction Motor Drive: Performances Analysis [J] . Ben Hamed Mouna ,Sbita Lassaad . 能源与动力工程（英文） . 2011,第1期
• 2. A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP [J] . Yu Guangming Wang Yu Yang Huazhong . 电子科学学刊：英文版 . 2011,第3期
• 3. 高频数字锁相环频率合成器设计 [C] . 胡焱 ,陈其周 ,王俊 . 全国第十一届DSP应用技术学术会议 . 2014
• 4. 基于FPGA的数字锁相环与直接数字频率合成器设计与实现 [A] . 雷鑫 . 2014