Reducing the latency time of a computer memory system in which instructions are processed in a non-ordered manner when cache memory has been accessed unsuccessfully by provision of multiple buffer slots for rearranging addresses

摘要

Device comprises multiple buffer slots (48) for rearranging addresses, in each of which an address is memorized corresponding to a number of data transmission lines, one or more cache slots that detects if a first data transmission into cache has been successful, and software associated with the cache slot to indicate if a requested data transmission line has already been requested by the hierarchical memory system. An Independent claim is made for a method for reducing memory latency time when cache access has been unsuccessful.