A method for identifying and removing false feedback loops in circuit synthesis

摘要

A circuit synthesis method includes the steps of converting a behavioural description describing a behaviour of calculation processing into a control data flowgraph (CDFG) describing a logic circuit at register transfer level (RTL) : assigning a plurality of calculations, at least one input and at least one output in the CDFG into a plurality of prescribed time slots: assigning the plurality of calculations, of data dependency edges, the at least one input and output respectively to a plurality of calculation devices, at least one register, input pin and output pin; and generating a plurality of paths corresponding to the plurality of data dependency edges: and detecting a feedback loop formed of at least two of the plurality of paths and at least one of the plurality of calculation devices: and re-assigning one calculation, which has been assigned to a first calculation device included in the feedback loop, to a second calculation device among the plurality of calculation devices, so as to delete the feedback loop.