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The ram bus ASIC tip/chip which is used for the ram bus memory system and this ram bus memory system which have high-speed test facility and the test manner null which uses

机译:用于具有高速测试设施和使用的测试方式的ram总线存储系统的ram总线ASIC技巧/芯片和该ram总线存储系统

摘要

A Rambus ASIC having a high speed testing function and a testing method thereof are disclosed, in which a high speed test of 500MHz or greater is realized using a low frequency testing system. The Rambus ASIC having a high speed testing function includes a Rambus ASIC chip constituting a master device, which includes an RAC with a first data input/output speed, a Rambus DRAM constituting a slave device, a test comparator for driving or comparing data at a second speed lower than the first data input/output speed through each I/O pin in the Rambus ASIC chip, an operating clock supply part for supplying an operating clock to the RAC of the Rambus ASIC chip by varying the operating clock in data writing and reading under the control of the frequency of the test comparator, and a test logic part for outputting data input/output test signals to the test comparator by temporarily storing and comparing data writing/reading signals in the Rambus DRAM.
机译:公开了一种具有高速测试功能的Rambus ASIC及其测试方法,其中使用低频测试系统实现500MHz或更高的高速测试。具有高速测试功能的Rambus ASIC包括构成主设备的Rambus ASIC芯片,该芯片包括具有第一数据输入/输出速度的RAC,构成从设备的Rambus DRAM,用于驱动或比较数据的测试比较器。通过Rambus ASIC芯片中的每个I / O引脚的第二速度低于第一数据输入/输出速度,该操作时钟提供部分用于通过改变数据写入和写入操作中的操作时钟来向Rambus ASIC芯片的RAC提供操作时钟。在测试比较器的频率控制下进行读取和测试逻辑部分,该测试逻辑部分用于通过在Rambus DRAM中临时存储和比较数据写入/读取信号来将数据输入/输出测试信号输出到测试比较器。

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