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IMPROVED METHOD FOR Cu ELECTROPLATING IN INTEGRATED CIRCUIT FABRICATION

机译:集成电路制造中电镀铜的改进方法

摘要

PROBLEM TO BE SOLVED: To provide a method for forming copper interconnects having low electroresistivity and high electromigration resistance by using copper electroplating.;SOLUTION: In the copper electroplating process, a negative potential is applied to a semiconductor wafer with the surface of the semiconductor wafer acting as the cathode. The anode is partially or wholly formed with copper. Both the anode and the semiconductor wafer are exposed to a solution comprising copper electrolytes. By reducing the temperature of the copper electrolyte solution below 25°C, the rate of self annealing grain growth increases reducing the final resistivity of the copper lines.;COPYRIGHT: (C)2003,JPO
机译:解决的问题:提供一种通过使用铜电镀形成具有低电阻率和高电迁移电阻的铜互连的方法。解决方案:在铜电镀工艺中,将负电势施加到具有半导体晶片表面的半导体晶片上充当阴极。阳极部分或全部由铜形成。阳极和半导体晶片都暴露于包含铜电解质的溶液中。通过将铜电解液的温度降低到25℃以下,晶粒的自退火速率会提高,从而降低了铜线的最终电阻率。; COPYRIGHT:(C)2003,JPO

著录项

  • 公开/公告号JP2003113494A

    专利类型

  • 公开/公告日2003-04-18

    原文格式PDF

  • 申请/专利权人 TEXAS INSTR INC TI;

    申请/专利号JP20020215033

  • 发明设计人 JIANG QING-TANG;LU JIONG-PING;

    申请日2002-07-24

  • 分类号C25D7/12;C25D21/00;H01L21/288;

  • 国家 JP

  • 入库时间 2022-08-22 00:17:02

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