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SEMICONDUCTOR DEVICE WHICH INCORPORATES MEMORY CHIP AND LOGIC CHIP, AND IN WHICH TEST OF MEMORY CHIP CAN BE PERFORMED

机译:包含存储器芯片和逻辑芯片的半导体设备,以及可以进行存储器芯片的测试的半导体设备

摘要

PROBLEM TO BE SOLVED: To perform effectively an operation test of a memory chip in a semiconductor device of a MCP (memory chip package) in which a logic chip and a memory chip arte mounted in a common package.;SOLUTION: In this semiconductor device incorporating a logic chip having the prescribed functions and a memory chip storing data in a common package, the logic chip and the memory chip are connected through terminals for memory access such as a control signal terminal, an address terminal, a data terminal, the logic chip has a logic circuit having the prescribed function and a memory chip test circuit performing an operation test of the memory chip. In a preferable embodiments, the logic chip has further a selector/output circuit selecting a memory access signal from the logic circuit and an access signal for memory test from the memory chip test circuit and outputting them to the terminal for memory access.;COPYRIGHT: (C)2003,JPO
机译:解决的问题:有效执行MCP(存储器芯片封装)的半导体器件中存储芯片的操作测试,其中逻辑芯片和存储芯片安装在同一封装中。包含具有规定功能的逻辑芯片和将数据存储在同一封装中的存储芯片,通过控制信号端子,地址端子,数据端子,逻辑端子等用于存储器访问的端子连接逻辑芯片和存储芯片。芯片具有具有规定功能的逻辑电路和进行存储器芯片的工作测试的存储器芯片测试电路。在优选的实施例中,逻辑芯片还具有选择器/输出电路,该选择器/输出电路选择来自逻辑电路的存储器访问信号和来自存储器芯片测试电路的用于存储器测试的访问信号,并将它们输出到用于存储器访问的端子。日本特许厅(C)2003

著录项

  • 公开/公告号JP2003077296A

    专利类型

  • 公开/公告日2003-03-14

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20010268918

  • 发明设计人 ISHIKAWA KATSUYA;

    申请日2001-09-05

  • 分类号G11C29/00;G01R31/28;G11C11/401;

  • 国家 JP

  • 入库时间 2022-08-22 00:17:02

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