AUTOMATIC FLOOR PLAN SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT, FLOOR PLAN METHOD THEREFOR, AND COMPUTER PROGRAM THEREFOR

摘要

PROBLEM TO BE SOLVED: To enable to design an optimal block set configuration and floor plan therefor in logical and physical views by organically merging the generation (logic circuit division) of blocks for floor plan and that floor plan (physical provision).;SOLUTION: A logic hierarchical structure tree is generated by extracting a logic hierarchical structure from an inputted design object circuit. Next, an initial block set is generated by respectively collecting the sets of gates included in the least significant logic hierarchy of the logic hierarchical structure tree into one block, and the rough initial floor plan of the initial block set is performed. Next, a new block set is generated by respectively collecting the sets of initial blocks proximately located in the initial rough floor plan. Next, the initial floor plan solution of the newly generated block set is generated. Finally, the final floor plan (block locating position or form determination) is performed by successively improving the initial floor plan.;COPYRIGHT: (C)2003,JPO