FLOOR PLAN GENERATING METHOD, FLOOR PLAN GENERATING DEVICE AND FLOOR PLAN GENERATING PROGRAM FOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a floor plan generating method, floor plan generating device and floor plan generating program capable of ensuring a wiring area according to wiring congestion degree and shortening the period required for LSI design.;SOLUTION: A floor plan area is divided into small sections, and the wiring congestion degree within each small section is estimated. Further, the shape of blocks is deformed according to the calculated wiring congestion degree so as not to overlap each other, and the wiring area according to the wiring congestion degree is ensured by this deformation of block shape.;COPYRIGHT: (C)2004,JPO