ASYNCHRONOUS SERIAL-TO-PARALLEL CONVERSION METHOD AND CONVERSION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To solve the problem of a VHDL(VHSIC hardware description language) description for an asynchronous serial-to-parallel conversion circuit adopting a conventional system that cannot normally drive a plurality of asynchronous serial-to-parallel conversion circuits because of increased clock skew when a built-in clock buffer cannot be used.;SOLUTION: Buffers 12, 13 distribute a serial clock (sr_-clk) into serial clocks sr_-clk3 and sr_-clk2 independently of each other, which are fed to FF 14 to FF 17 configuring a 1st shift register for odd data and FF 18 to FF 21 configuring a 2nd shift register for even data. Thus, intentional insertion of an individual buffer is described in the VHDL so that the same shift register uses a clock outputted from the same buffer so as to decrease clock skew.;COPYRIGHT: (C)2003,JPO