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DEVICE FOR FPSA AND ITS DESIGN METHOD

机译:FPSA的装置及其设计方法

摘要

PROBLEM TO BE SOLVED: To effectively design a FPSA device in a short time by preventing the prolongation of a design time and a redesign time due to an additional function. ;SOLUTION: This FPSA device comprises a plurality of basic cells 2 to be a sequencer, the basic cells 2 having a sequence table 11 that has a preset number of slots to store simple commands, and has a structure where these basic cells 2 are connected by a network circuit. The device for this FPSA comprises a clock multiplying circuit for generating an internal clock that is an external clock multiplied by an arbitrary number, a means for processing one command assigned in each basic cell 2 in one period of the internal clock, a means for processing in accordance with a command row by making the sequence table 11 of each basic cell 2 hold the command row comprising a plurality of commands, an arithmetic memory part 13 for holding an arithmetic result of each basic cell 2, and a means for programming the multiplication number of the clock and the sequence table 11.;COPYRIGHT: (C)2003,JPO
机译:要解决的问题:通过防止由于附加功能而延长设计时间和重新设计时间,可以在短时间内有效地设计FPSA器件。 ;解决方案:该FPSA设备包括多个要用作定序器的基本单元2,基本单元2具有序列表11,该序列表具有用于存储简单命令的预设数量的插槽,并且具有连接这些基本单元2的结构通过网络电路。用于该FPSA的装置包括:时钟倍频电路,用于生成内部时钟,该内部时钟是由外部时钟乘以任意数字而得到的;用于在内部时钟的一个周期中处理在每个基本单元2中分配的一个命令的装置;用于处理的装置。通过使每个基本单元2的序列表11保持包括多个命令的命令行来根据命令行,用于保持每个基本单元2的算术结果的算术存储部13以及用于对乘法进行编程的装置时钟编号和顺序表11.; COPYRIGHT:(C)2003,JPO

著录项

  • 公开/公告号JP2002353318A

    专利类型

  • 公开/公告日2002-12-06

    原文格式PDF

  • 申请/专利权人 LOGIC RESEARCH:KK;

    申请/专利号JP20010161388

  • 发明设计人 AKABOSHI HIROTERU;TSUCHIYA TADAAKI;

    申请日2001-05-29

  • 分类号H01L21/82;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 00:12:19

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