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Frequency divider with reduced power consumption, apparatus based thereon, and method for power efficient frequency divider
Frequency divider with reduced power consumption, apparatus based thereon, and method for power efficient frequency divider
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机译:具有降低的功耗的分频器,基于该分频器的设备以及用于省电分频器的方法
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摘要
Apparatus comprising a frequency dividing cell (42) with a prescaler logic, an end-of-cycle logic, a clock input for receiving an input clock (CKin) with frequency fn, a clock output for providing an output clock (CKout) with frequency fm to a subsequent cell (43), a mode control input for receiving a mode control input signal (MDin) from the subsequent cell (43), and a mode control output for providing a mode control output signal (MDout) to a preceding cell (41). The end-of-cycle logic of the frequency dividing cell (42) has a switchable tail current source. This switchable tail current source allows the biasing current of the end-of-cycle logic to be switched off in order to save power.
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