Frequency divider with reduced power consumption, apparatus based thereon, and method for power efficient frequency divider

摘要

Apparatus including a frequency dividing cell (42) with a prescaler logic, an end-of-cycle logic, a clock input for receiving an input clock (CKin) with frequency fn, a clock output for providing an output clock (CKout) with frequency fm to a subsequent cell (43), a mode control input for receiving a mode control input signal (MDin) from the subsequent cell (43), and a mode control output for providing a mode control output signal (MDout) to a preceding cell (41). The end-of-cycle logic of the frequency dividing cell (42) has a switchable tail current source. This switchable tail current source allows the biasing current of the end-of-cycle logic to be switched off in to save power.