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Load balanced scalable network gateway processor architecture

机译:负载均衡的可扩展网络网关处理器架构

摘要

A network gateway processor architecture including a scalable array of compute processors that function to convert inbound data packets to outbound data packets, an ingress processor coupleable to a first network to receive the inbound data packets and coupled to provide the inbound data packets to the compute processors, and an egress processor coupleable to a second network and coupled to the compute processors to collect and forward the outbound data packets to the second network. The ingress processor distributes inbound data packets to the compute processors based on a least load value selected from current load values determined for the respective compute processors of the scalable array. The current load values represent estimated processing completion times for the respective compute processors of the scalable array of compute processors. Preferably, the current load values are dynamically derived with respect to the size of the inbound data packets and the performance of the respective compute processors.
机译:一种网络网关处理器体系结构,包括可伸缩的计算处理器阵列,其功能是将入站数据包转换为出站数据包;入口处理器,其可耦合到第一网络以接收入站数据包,并耦合以将入站数据包提供给计算处理器以及可耦合到第二网络并耦合到计算处理器的出口处理器,以收集出站数据分组并将其转发到第二网络。入口处理器基于从为可伸缩阵列的各个计算处理器确定的当前负载值中选择的最小负载值,将入站数据分组分发到计算处理器。当前负载值表示针对可缩放计算处理器阵列的各个计算处理器的估计处理完成时间。优选地,关于入站数据分组的大小和各个计算处理器的性能来动态地得出当前负载值。

著录项

  • 公开/公告号US2003074388A1

    专利类型

  • 公开/公告日2003-04-17

    原文格式PDF

  • 申请/专利权人 PHAM DUC;PHAM NAM;NGUYEN TIEN LE;

    申请/专利号US20010976229

  • 发明设计人 NAM PHAM;DUC PHAM;TIEN LE NGUYEN;

    申请日2001-10-12

  • 分类号G06F9/00;G06F15/173;

  • 国家 US

  • 入库时间 2022-08-22 00:11:13

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