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Unified database system to store, combine, and manipulate clock related data for grid-based clock distribution design
Unified database system to store, combine, and manipulate clock related data for grid-based clock distribution design
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机译:统一的数据库系统,用于存储,组合和处理与时钟相关的数据,用于基于网格的时钟分配设计
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摘要
A method and apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution. The method includes partitioning the complete clock net into a global clock net and a plurality of local clock nets, simulating a load for each of the local clock nets, simulating the global clock net, and combining the simulations to form the complete clock net. The method may further include evaluating the combination to determine whether the results converge and storing the simulation results in a Clock Data Model. When the results do not converge, the method re-simulates at least one of the local clock nets and re-simulates the global clock net. The Clock Data Model collects, manages, retrieves, and queries all of the simulation information. The method may further analyze the complete clock net to predict the clock skew for a given data transfer path for potential redesign.
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机译:为具有基于网格的时钟分布的微处理器设计确定时钟插入延迟的方法和装置。该方法包括将完整的时钟网划分为全局时钟网和多个本地时钟网,模拟每个本地时钟网的负载,模拟全局时钟网,以及将模拟组合以形成完整的时钟网。该方法可以进一步包括评估组合以确定结果是否收敛并将仿真结果存储在时钟数据模型中。当结果不收敛时,该方法重新模拟至少一个本地时钟网并重新模拟全局时钟网。 Clock Data Model收集,管理,检索和查询所有模拟信息。该方法可以进一步分析完整的时钟网以预测给定数据传输路径的时钟偏斜,以进行潜在的重新设计。
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