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OVERLAY SHIFT CORRECTION FOR THE DEPOSITION OF EPITAXIAL SILICON LAYER AND POST-EPITAXIAL SILICON LAYERS IN A SEMICONDUCTOR DEVICE
OVERLAY SHIFT CORRECTION FOR THE DEPOSITION OF EPITAXIAL SILICON LAYER AND POST-EPITAXIAL SILICON LAYERS IN A SEMICONDUCTOR DEVICE
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机译:在半导体器件中沉积表观硅层和表观后硅层的叠加偏移校正
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摘要
Correction of overlay shift of an epitaxial silicon layer deposited on a semiconductor wafer, and of post-epitaxial silicon layers subsequently deposited, is disclosed. When an epitaxial silicon layer of a given thickness is deposited, the zero mark coordinates for the deposition are shifted relative to alignment marks on the wafer by a distance based on the thickness of the layer. The distance is preferably proportional to the thickness of the epi layer. This prevents overlay shift of the epi layer. For post-epitaxial silicon layers subsequently deposited, preferably except for the first post-epi layer, a clear out process is initially performed to maintain the alignment marks on the semiconductor wafer. In this way, overlay shift, or misalignment, of the post-epi layers is also prevented.
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