DC-tolerant bit slicer and method

摘要

A bit slicer circuit and method detect the peak of the differential slope in a demodulated data signal received via a wireless data system, so that bit slicing can be insensitive to DC fluctuations. This is accomplished by detecting when the demodulated signal transitions by more than a predetermined threshold value V_th during each symbol period, and determining the polarity of a detected transition. A latch is set and a logic “1”, is output when the polarity of a detected transition is negative; the latch is reset and a logic “0” is output when the polarity is positive.