METHOD FOR IMPROVING A TIMING MARGIN IN AN INTERGRATED CIRCUIT BY SETTING A RELATIVE PHASE OF RECEIVE/TRANSMIT AND DISTRIBUTED CLOCK SINGLS

摘要

An embodiment of the invention includes an apparatus that has a first clock on a memory controller hub that is set to a first clock receive time and a second clock on the memory controller hub set to a first clock transmit time. A first data is sent from the memory to the memory controller hub. A second data is sent from the memory to the memory controller hub wherein the second data is checked. At least one of the first clock and the second clock has at least one of a second clock receive time and a second clock transmit time adjusted.