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Method and system for synthesizing a circuit representation into a new circuit representation having greater unateness

机译:用于将电路表示合成为具有更大统一性的新电路表示的方法和系统

摘要

Method, system and computer-executable code are disclosed for synthesizing a representation of a circuit into a new circuit representation having greater unateness. The invention includes partitioning a circuit representation to obtain a representation of at least one sub-circuit, recursively decomposing the representation of the at least one sub-circuit into a sum-of-products or product-of-sums representation having greater unateness than the representation of the at least one sub-circuit, merging the sum-of-products or product-of-sums representation into the circuit representation to form a new circuit representation, and repeating until a desired level of unateness for the new circuit representation is achieved. Algebraic division is implemented to merge common expressions of the sum-of-products or product-of-sums representations. A zero-suppressed binary decision diagram is implemented to recursively decompose the representation of the sub-circuit.
机译:公开了用于将电路的表示合成为具有更大统一性的新电路表示的方法,系统和计算机可执行代码。本发明包括分割电路表示以获得至少一个子电路的表示,将所述至少一个子电路的表示递归分解为乘积总和或乘积总和,所述总和大于所述至少一个子电路的表示,将乘积和或乘积表示合并到电路表示中以形成新的电路表示,并重复直到达到新电路表示的期望的不协调程度。实现代数除法以合并乘积和或乘积表示的通用表达式。实现零抑制二进制决策图以递归分解子电路的表示。

著录项

  • 公开/公告号US2002178432A1

    专利类型

  • 公开/公告日2002-11-28

    原文格式PDF

  • 申请/专利权人 KIM HYUNGWON;HAYES JOHN P.;

    申请/专利号US20010931131

  • 发明设计人 HYUNGWON KIM;JOHN P. HAYES;

    申请日2001-08-16

  • 分类号G06F17/50;G06F9/45;

  • 国家 US

  • 入库时间 2022-08-22 00:08:59

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