Parallel push algorithm detecting constraints to minimize clock skew
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机译:并行推送算法检测约束以最大程度地减少时钟偏斜
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摘要
A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.
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