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Memory controller for supporting a plurality of different memory accesse modes
Memory controller for supporting a plurality of different memory accesse modes
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机译:用于支持多种不同的存储器访问模式的存储器控制器
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摘要
A common DRAM controller is provided for supporting a plurality of memory types such as double data rate or quad data rate mode or types. The controller is adapted to use a number of clock signals to process data. The controller can further delay the data for a predetermined time period and capture the same.
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