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Partial selection of passive element memory cell sub-arrays for write operations

机译:无源元件存储单元子阵列的部分选择用于写操作

摘要

A memory array is subdivided into many sub-arrays which are separately selectable in groups, with each group containing one or more sub-arrays. The various data bits of a data set are physically spread out and mapped into a large number of associated sub-array groups. All the associated sub-array groups are preferably selected during a read cycle to simultaneously read the various bits of the data set, but when writing the data set, a smaller number of sub-array groups are activated during each of several write cycles to simultaneously write only a portion of the data set. Consequently, the read bandwidth remains high and is driven by the number of bits simultaneously read, but the write power is reduced since during each write cycle fewer bits are written. Such a memory array is particularly advantageous with passive element memory cells, such as those having antifuses.
机译:存储器阵列可细分为许多子阵列,可分别在组中选择子阵列,每组包含一个或多个子阵列。数据集的各种数据位在物理上分散开并映射到大量关联的子阵列组中。优选地,在读取周期期间选择所有相关联的子阵列组以同时读取数据集的各个位,但是当写入数据集时,在几个写入周期中的每一个期间激活较少数量的子阵列组以同时只写一部分数据。因此,读取带宽保持较高,并由同时读取的位数驱动,但由于在每个写入周期内写入的位数较少,因此降低了写入功率。这种存储阵列对于无源元件存储单元,例如具有反熔丝的那些,特别有利。

著录项

  • 公开/公告号US6633509B2

    专利类型

  • 公开/公告日2003-10-14

    原文格式PDF

  • 申请/专利权人 MATRIX SEMICONDUCTOR INC.;

    申请/专利号US20020310225

  • 发明设计人 ROY E. SCHEUERLEIN;MATTHEW P. CROWLEY;

    申请日2002-12-05

  • 分类号G11C80/00;

  • 国家 US

  • 入库时间 2022-08-22 00:06:56

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