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Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells
Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells
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机译:与标准CMOS单元兼容的低泄漏PMOS片上去耦电容器单元
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摘要
An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.
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