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An On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS

机译：一种用于65nm CmOs单个标准单元内部延迟变化测量的片上特征分析系统

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1. On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS [J] . Zhang X., Ishida K., Fuketa H., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2012,第10期

机译：片内测量系统，用于在65 nm CMOS中单个标准单元的片内延迟变化
2. A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells [J] . Mostafa H., Anis M., Elmasry M. Circuits and Systems I: Regular Papers, IEEE Transactions on . 2010,第6期

机译：面向设计的软错误率变化模型，同时考虑了亚微米CMOS SRAM单元中的芯片间和芯片内变化
3. A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application [J] . Nguyen Ngoc MAI KHANH, Masahiro SASAKI, Kunihiro ASADA IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2011,第12期

机译：具有片上抖动和脉冲延迟调整功能的65nm CMOS完全集成冲击波天线阵列，用于毫米波有源成像应用
4. An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS [C] . Xin Zhang, Ishida K., Takamiya M., 2011 16th Asia and South Pacific Design Automation Conference . 2011

机译：片上表征系统，用于在65 nm CMOS中测量单个标准单元的晶粒内延迟变化
5. Modeling of deterministic within-die variation in timing analysis, leakage current analysis, and delay fault diagnosis. [D] . Choi, Munkang. 2007

机译：在时序分析，漏电流分析和延迟故障诊断中确定性的模内变化建模。
6. A 0.18 μm CMOS LDO Regulator for an On-Chip Sensor Array Impedance Measurement System [O] . Jorge Pérez-Bailón, Alejandro Márquez, Belén Calvo, 2018

机译：用于片上传感器阵列阻抗测量系统的0.18μmCMOS LDO稳压器
7. A 65-nm CMOS Fully Integrated Analysis Platform Using an On-Chip Vector Network Analyzer and a Transmission-Line-Based Detection Window for Analyzing Circulating Tumor Cell and Exosome [O] . Kiichi Niitsu, Taiki Nakanishi, Shunya Murakami, 2019

机译：使用片上矢量网络分析仪和基于传输线的检测窗口的65nm CMOS完全集成的分析平台，用于分析循环肿瘤细胞和外来

An On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS

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