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System and method for performing timing analysis, including error diagnosis, signal tracking and clock skew

机译:用于执行时序分析的系统和方法,包括错误诊断,信号跟踪和时钟偏斜

摘要

A method for performing timing analysis comprising inputting circuit timing information for a circuit, including temporal constraints between events of a desired circuit operation. A timing diagram representing the desired circuit operation, based on the circuit timing information is generater. All violated constraints within said timing diagram are identified. The method forces no violations of said violated constraints by designating the violated constraints as Non-Breakable (NB) constraints, such that a time difference from a source event to a destination event which defines said NB constraint is no less than a minimum bound and no more than a maximum bound of a linear constraint representing a timing requirement between the source and the destination events.
机译:一种用于执行时序分析的方法,包括输入电路的电路时序信息,包括期望的电路操作的事件之间的时间约束。生成基于电路时序信息的表示期望的电路操作的时序图。识别出所述时序图中的所有违反的约束。该方法通过将违反的约束条件指定为不可破坏(NB)约束来强制不违反所述违反的约束条件,使得从源事件到定义所述NB约束条件的目的地事件的时间差不小于最小界限且不小于大于表示源事件和目标事件之间的时间要求的线性约束的最大界限。

著录项

  • 公开/公告号US6594806B1

    专利类型

  • 公开/公告日2003-07-15

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US20000588539

  • 发明设计人 ALBERT E. CASAVANT;

    申请日2000-06-07

  • 分类号G06F175/00;

  • 国家 US

  • 入库时间 2022-08-22 00:06:13

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