Design method and system for providing transistors with varying active region lengths

摘要

A method (40) of designing a circuit comprising a plurality of transistors (10, 46_T, 60_T). Each transistor of the plurality of transistors comprises an active region, a gate (G₁, G₂), a first source/drain (S/D₁, S/D₃) in the active region, a second source/drain in the active region, and at least one contact in each of the first source/drain and the second source/drain. The method comprises various steps. The method specifies a first set of distances for each transistor in a first set (10) of transistors in the plurality of transistors, wherein the first set of distances comprises a gate length (L_g), a gate width (W_g), and a distance representative of one or both of a first contact-to-edge distance (CTE₁) and a first contact-to-gate distance (CTG₁). The method also specifies (46) a second set of distances for each transistor in a second set (46_T, 60_T) of transistors in the plurality of transistors, wherein the second set of distances comprises a gate length (L_g), a gate width (W_g), and a distance representative of one or both of a second contact-to-edge distance (CTE₂) and a second contact-to-gate distance (CTG₂). For the method specifications, either or both the second contact-to-edge distance is greater than the first contact-to-edge distance and the second contact-to-gate distance is greater than the first contact-to-gate distance. Also for the method specifications, for each transistor in the second set of transistors, the step of specifying a second set of distances is responsive to a determination (44, 48) of a benefit from a larger drive current to be provided by the transistor in the second set of transistors.