Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction

摘要

An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor. The apparatus computes a speculative result associated with an arithmetic operation, where the arithmetic operation is prescribed by a preceding micro instruction that is yet to generate a result. The apparatus utilizes the speculative result to configure a speculative address operand that is provided to an address-dependent micro instruction The apparatus includes speculative operand calculation logic and an update forwarding cache. The speculative operand calculation logic performs the arithmetic operation to generate the speculative result prior to when execute logic executes the preceding micro instruction to generate the result. The update forwarding cache is coupled to the speculative operand calculation logic and temporarily stores the speculative result, where address-dependent micro instructions can retrieve a configured speculative address operand, thereby permitting them to proceed without incurring delay.