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Digital designs optimized with time division multiple access technology

机译:采用时分多址技术优化的数字设计

摘要

A system and method for designing a digital circuit. The method includes identifying a single phase digital circuit implementing a desired function and operating at a first rate and determining a number of copies of the single phase digital circuit that are required for the digital circuit. Each copy of the single phase circuit is a phase and operates at a lesser rate wherein the sum of the lesser rates is less than or equal to the first rate. The method includes identifying the state devices within the single phase digital circuit, replacing each state device in the single phase digital circuit with a multiphase state saving device and providing control signals to each multiphase state saving device to control the reading and writing of state information for each phase into and out of a respective multiphase state saving device.
机译:一种用于设计数字电路的系统和方法。该方法包括:识别实现期望功能并以第一速率操作的单相数字电路,以及确定该数字电路所需的单相数字电路的副本数量。单相电路的每个副本都是一个相,并且以较小的速率工作,其中较小的速率之和小于或等于第一速率。该方法包括:识别单相数字电路中的状态设备;用多相状态保存设备替换单相数字电路中的每个状态设备;以及向每个多相状态保存设备提供控制信号,以控制状态信息的读取和写入。每个相进入和退出各自的多相状态保存设备。

著录项

  • 公开/公告号US6556045B2

    专利类型

  • 公开/公告日2003-04-29

    原文格式PDF

  • 申请/专利权人 CISCO TECHNOLOGY INC.;

    申请/专利号US20010826563

  • 发明设计人 EARL T. COHEN;

    申请日2001-04-04

  • 分类号G06F73/80;H03K191/73;

  • 国家 US

  • 入库时间 2022-08-22 00:04:58

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