Area efficient redundancy multiplexer circuit technique for integrated circuit devices providing significantly reduced parasitic capacitance

摘要

An improved integrated circuit area efficient redundancy multiplexer circuit technique provides similar functionality to conventional CMOS transmission, or “pass” gates while concomitantly reducing circuit complexity, the die area necessary to support redundant elements and complementary control signals in memory device ICs and undesired parasitic capacitance. The technique of the present invention effectuates this end by utilizing the on-chip boosted voltage levels (V_pp) which are generally available in integrated circuit memory devices to supply the voltage for the control signal applied to a single N-channel transistor pass gate instead of the conventional supply voltage level of V_cc. The V_pp voltage and circuit ground (“GND”) are then utilized as the logic “high” and “low” signal levels respectively. This use is made possible due to the fact that these control signals operate at a direct current (“DC”) level after device power-up. When the integrated circuit has powered-up and is stabilized (and after the redundancy has been programmed), the signal levels of the single transistor N-channel pass gates are stabilized. The significant reduction in undesired parasitic capacitance that is also provided allows for higher throughput speeds in the address and data paths.