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High speed microprocessor zero detection circuit with 32-bit and 64-bit modes
High speed microprocessor zero detection circuit with 32-bit and 64-bit modes
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机译:具有32位和64位模式的高速微处理器零检测电路
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摘要
A zero-detection circuit is provided. The zero-detection circuit includes a plurality of transistor stacks. Each transistor stack includes an input transistor and a clocked transistor. Each of the plurality of input transistors receives a data input. An intermediate node is connected to the input transistor stacks. An output stage is coupled to the intermediate node providing an output. The output stage includes a bit selection control circuit receiving a bit selection signal. The bit selection control circuit provides a zero level output of the output stage responsive to a predefined bit selection signal. The transistor stacks comprise silicon-on-insulator (SOI) transistors.
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